This application claims priority to Korean Patent Application No. 2003-0095140, filed on Dec. 23, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to fabrication of a MOS (metal oxide semiconductor) transistor with a trench-type gate and an asymmetric channel region for minimizing undesired short channel effects.
2. Description of the Related Art
A MOSFET (metal oxide semiconductor field effect transistors) is a commonly used device in integrated circuits. Dimensions of integrated circuit devices are desired to be further minimized as known to one of ordinary skill in the art. The channel length of a MOSFET is reduced to deep sub-micron dimensions for enhanced operating speed and current drive capability of the MOSFET.
With such decreased channel length, the depletion regions of the source and drain encroach into the channel resulting in reduction of the effective channel length and the threshold voltage of the MOSFET. Such reduced effective channel length and threshold voltage disadvantageously lead to short channel effects as the gate control function is degraded for the MOSFET.
For preventing such short channel effects, shallow source and drain junctions and a doped region under the channel are formed. The doped region is doped with a dopant having a conductivity that is opposite to that for the source and drain junctions. However, a high electric field is applied for such a MOSFET resulting in hot carrier injection into the gate dielectric which becomes degraded.
For preventing such hot carrier generation, LDD (Lightly Doped Drain) structures are provided. A LDD structure acts as a buffer region with a low dopant concentration toward the channel region from the source/drain junction having higher dopant concentration.
Nevertheless with ever decreasing channel length, even the LDD structures provide limited reduction of short channel effects and hot carrier injection. Furthermore, during operation of the MOS transistor, undesired punch-through may also occur even with such LDD structures.
Because of such disadvantageous effects from a short channel, a MOS transistor is formed with a trench-type gate for lengthening the channel especially for a low area of the MOS transistor. Alternative terms for the trench-type gate are recess-type or groove-type gate.
FIGS. 1A to 1Q are cross-sectional views illustrating the steps of fabricating such a MOS transistor with a trench-type gate according to the prior art. Referring to FIG. 1A, a first pad oxide layer 12 and a first hard mask layer 14 are sequentially formed on a semiconductor substrate 10. Referring to FIGS. 1A and 1B, photoresist is deposited on the first hard mask layer 14, and is then patterned to partially expose the hard mask layer 14. Exposed regions of the first hard mask layer 14 are etched away to define an active device region ACT within the semiconductor substrate 10. Thereafter, the photoresist is removed.
Referring to FIGS. 1B and 1C, exposed portions of the first pad oxide layer 12 and the semiconductor substrate 10 are sequentially etched. By thus using the first hard mask layer 14 as an etch mask, a first trench T1 is formed to surround the active device region ACT within the semiconductor substrate 10.
Referring to FIGS. 1C and 1D, an insulating material 16 is formed within the first trench T1. Such insulating material 16 is formed in a thermal oxidation process with the first hard mask layer 14 and the first pad oxide layer 12 being oxidation prevention masks. Thereafter, the first hard mask layer 14 and the first pad oxide layer 12 are removed by a chemical mechanical polishing (CMP) process or an etch back process. After such planarization, a STI (shallow trench isolation) structure 16 is formed to surround the exposed active device region ACT of the semiconductor substrate 10.
Referring to FIGS. 1D and 1E, a P-type dopant is implanted at high energy with relatively low concentration into the semiconductor substrate 10 to form a channel region of the MOS transistor. This channel region is formed substantially into the semiconductor substrate 10, except the STI structure 16, and so does not have a specific reference number in the drawings.
Referring to FIGS. 1E and 1F, a second pad oxide layer 18 and a second hard mask layer 20 are sequentially formed on the semiconductor substrate 10. Referring to FIGS. 1F and 1G, photoresist is deposited and patterned on the second hard mask layer 20 in a photolithography process. Thereafter, exposed portions of the second hard mask layer 20 are etched to pattern the second hard mask layer 20. Next, the photoresist is removed.
Referring to FIGS. 1G and 1H, exposed portions of the second pad oxide layer 18 and the semiconductor substrate 10 are sequentially etched. By thus using the second hard mask layer 20 as an etch mask, a second trench T2 having a predetermined depth is formed within the active device region ACT.
Referring to FIGS. 1H and 1I, the second hard mask layer 20 and the second pad oxide layer 18 are removed to expose surfaces of the semiconductor substrate 10 including the walls of the second trench T2. Referring to FIGS. 1I and 1J, a gate dielectric 22 is formed on any exposed surfaces of the semiconductor substrate 10 including the walls of the second trench T2.
Referring to FIGS. 1J and 1K, a gate electrode 24, a metal layer 26, and an upper gate insulating layer 28 are sequentially deposited. Referring to FIG. 1K, the gate electrode 24 fills the second trench T2.
Referring to FIGS. 1K and 1L, photoresist is deposited and patterned on the upper gate insulating layer 28 to form the gate insulating structure 28, the metal layer 26, and the gate electrode 24 of a gate stack 30 on a gate region G. The portions of the gate insulating material 28, the metal layer 26, and the gate electrode 24 disposed over the source and drain regions S and D and the STI structure 16 are etched away.
Referring to FIGS. 1L and 1M, an N-type dopant is implanted into the source and drain regions S and D of the semiconductor substrate 10 with a relatively low concentration to form LDD (lightly doped drain) regions 32. The gate stack 30 acts as an ion implantation mask in FIG. 1N.
Referring to FIGS. 1M and 1N, a spacer 34 comprised of silicon nitride is formed at sidewalls of each gate stack 30. Referring to FIGS. 1N and 1O, an N-type dopant is implanted into the source and drain regions S and D of the semiconductor substrate 10 with a relatively high concentration to form source and drain junctions 36. The gate stacks 30 and the spacers 34 act as ion implantation masks in FIG. 1O.
Referring to FIGS. 1O and 1P, the portions of the gate dielectric 22 on the source and drain regions S and D are removed. Referring to FIGS. 1P and 1Q, conductive material such as polysilicon doped with N-type dopant is blanket deposited and planarized until the gate insulating structure 28 is exposed to form source and drain electrodes 38 on the source and drain regions S and D, respectively.
Subsequently, a first interlayer insulation layer is deposited, and a portion of the first interlayer insulation layer above the source region S is removed to form a source contact hole. A bit line contact fills the source contact hole to be electrically coupled to the source electrode 38 formed on the source region S.
Thereafter, a second interlayer insulation layer is deposited, and a portion of the first and second interlayer insulation layers above the drain region D is removed to form a drain contact hole. A storage electrode fills the drain contact hole to be electrically coupled to the drain electrode 38 formed on the drain region D. Such a storage electrode is part of a data storage capacitor also having a dielectric layer and a plate electrode when the MOS transistor of FIG. 1Q is for a DRAM (dynamic random access memory) cell. However, the MOS transistor of FIG. 1Q may be used within other types of integrated circuits.
Unfortunately, the prior art MOS transistor formed according to FIGS. 1A to 1Q may still exhibit short channel effects. For example, when the critical dimensions (CD) including the depth of the second trench T2 are reduced, the depth of the source and drain junctions 36 with the relatively higher dopant concentration may not be correspondingly reduced, resulting in increased short channel effects.
In addition, if the depth of the LDD regions 32 approaches the bottom of the second trench T2, the length of the channel is shortened resulting in increased short channel effects. On the other hand, if the depth of the LDD regions 32 is reduced for decreasing short channel effects, the concentration of the N-type impurity is increased in turn resulting in increase of junction leakage current in the drain region D. Such higher junction leakage current in the drain region D degrades the refresh characteristics of the cell capacitor coupled to the drain region D.
Nevertheless, the MOS transistor with the trench-type gate is desired for the lengthened channel to decrease short channel effects. Thus, the MOS transistor with the trench-type gate but without disadvantages of the prior is desired for integrated circuits of high density.